DFM of Strained-Engineered MOSFETs Using Technology CAD

Abstract

Problem statement: In this study, a systematic study based on Technology CAD (TCAD) was taken up for the design and Virtual Wafer Fabrication (VWF) of strain-engineered MOSFETs in Si CMOS technology. Approach: A simple manufacturable process recipe was developed to induce uniaxial stress in channel region to obtain enhanced performance in CMOS in 45 nm technology node. Results: Using Synopsys Sentaurus Process simulation tool, high dopant activation and low Transient Enhanced Diffusion (TED) during processing are fully captured. A physics-based mobility model had been developed and implemented in Synopsys Sentaurus Device tool. Sentaurus Device was used to simulate device DC and AC characteristics and also to extract V_th, I_on and I_off. Conclusion: Optimum process conditions required to meet a set of device specifications had been achieved via the Design of Experiment (DoE) study. Process Compact Model (PCM) was used for performance and manufacturability optimization.