Design of an 8-bit Incremental ADC

Abstract

This technical report demonstrated a design an 8-bit switched-capacitor incremental ADC in UMC 0.13 μm CMOS. The design requirements are Supply voltage: 1.2V, Reference voltage (Vref): 1V, Resolution: 8 bits, Output data rate: 100 samples per second and Input voltage range: 0V to 1V. Furthermore, the determine the architecture of incremental A/D converter involved in fuzzy theory. The output waveforms of the clock generator plot with a proper time scale. In the result, we showed the digital outputs and plot the waveforms at the comparator’s output for three DC input values: One near 0V, one near Vref/2 and one near Vref. The exact DC values give the offset and gain errors of proposed circuit, supported by simulation results. We also simulated the DNL and INL using a histogram method and give the plots of the DNL and INL of the ADC for all output. Finally, we conclude the case report with a discussion of results (comparison, problems, solution, possible improvements, etc.).