Effect of Load and Routing Protocols on Networks on Chip (NoC): An Analysis
- 1 Department of Computer Science and Engineering, Chitkara University Institute of Engineering and Technology, Chitkara University, Punjab, India
- 2 Department of Computer Science, College of Computer Science and Engineering, Taibah University, Madinah, Saudi Arabia
- 3 Department of Computer Science and Engineering, Graphic Era (Deemed to be University), Dehradun, India
- 4 Department of Computer Science and Information, Taibah University, Madinah, Saudi Arabia
- 5 Faculty of Computer Science and Informatics, Berlin School of Business and Innovation, Germany, France
Abstract
Communication infrastructure for multi-core Systems-on-Chip (SoCs) is provided by Network-on-Chip (NoC). Point-to-Point (P2P) and bus-based communication systems are NoCs and are two communication channels of NoC that can probably overcome the scalability and performance restrictions of NoC. Latency and throughput are two of the essential characteristic metrics measured for a routing algorithm that affect the performance of a given NoC. This study evaluated and compared static and dynamic routing algorithms Dijkstra and distance vector on the scale of increasing flit length and network traffic. In a network, considering the effects of topology, traffic, buffer, and packet size, the dynamic algorithm performs better than a static algorithm on the network's performance. Moreover, the effect of increased network traffic on throughput and average packet delay with the increase in network size in a fixed MS topology and distance vector routing protocol has been evaluated. The results show that while using the Dijkstra algorithm, the average packet delay reached 50-60 packets/cycle in comparison to the Distance Vector where it reached a maximum of 40 packets/cycle in 4 different topologies. Throughput is achieved up to 100% in both algorithms using various topologies. In only MS topology, throughput reached 100% but packet delay increased to 400 pkts/cycle with an increase in network size.
DOI: https://doi.org/10.3844/jcssp.2024.1376.1387
Copyright: © 2024 Shaily Jain, Chander Prabha, Ayman Noor, Prakash Srivastava, Mohammad Zubair Khan and Priyadarshini Pattanaik. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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Keywords
- Multiprocessor System on a Chip
- Networks on a Chip
- MS Topology
- TS Topology
- BFT Topology
- Extended BFT Topology
- Flit
- Routing Algorithm
- Dijkstra
- Distance Vector